This relates generally to—transistors for integrated circuits, and particularly to transistors for stacked die configuration.
Modern electronic devices such as cellular telephones, cameras, and computers often include integrated circuits comprising transistors. Integrated circuits may be fabricated on single semiconductor wafers or a plurality of semiconductor wafers bonded to form a stacked semiconductor wafer. Single and stacked wafer integrated circuits include memory, processor, and digital image sensors. A stacked wafer and a stacked die integrated circuit include two silicon substrates stacked one above the other in a 3D configuration. One or more of the silicon substrates may include Silicon-On-Insulator (SOI) device structures. An image sensor includes a two-dimensional array of image sensing pixels. Each pixel typically includes a photosensitive element such as a photodiode that receives incident photons (light) and converts the photons into electrical signals. Configurations of a stacked imaging system in which a CMOS image sensor die is stacked on top of a digital signal processor (DSP) have been developed to help separate the formation of the analog image sensor circuitry such as photodiode structures and the formation of the digital pixel transistor circuitry into separate integrated circuit dies.
In one conventional stacked arrangement as described by Coudrain et al. (see, “Towards a Three-Dimensional Back-Illuminated Miniaturized CMOS Pixel Technology using 100 nm Inter-Layer Contacts,” incorporated herein as a reference), a backside illuminated silicon wafer is monolithically bonded to Silicon on Insulator (SOI) pixel transistors. Photodiodes are first formed in the silicon wafer, which is then bonded and thinned down to construct the SOI pixel transistors above the photodiodes. Formed in this way, the area above the photodiodes is occupied by the SOI pixel transistor (which restricts metal line routing for 3D logic integration), and the thermal cycles that are used to form the SOI transistors can negatively affect the doping of the photodiode and degrade well capacity. Moreover, the photodiodes and the SOI pixel transistors are bound by the same CMOS processing limitations.
In another conventional stacked arrangement as described by Saraswat et al. (see, “3-Dimensional ICs: Motivation, Performance Analysis and Technology,” incorporated herein as a reference), a fully processed pixel wafer is adhesively bonded to a fully processed analog/digital companion wafer. Forming a stacked image system in this way, however, is costly since both wafers require expensive transistor and metal processing steps, offers poor wafer-to-wafer interconnect density, and requires use of large and deep through-silicon via connections that affect color-filter-array (CFA) processing.
It is within this context that the embodiments described herein arise.